1. Field of the Invention
The present invention relates to packaging processes, and more particularly, to a method for fabricating a package structure having at least an electronic element.
2. Description of Related Art
Along with the progress of semiconductor packaging technologies, various package types have been developed for semiconductor devices. To improve electrical performances and save spaces, various 3D packaging technologies such as fan-out package on package (PoP) structures have been developed to meet the requirement of greatly increased I/O counts of semiconductor chips and integrate integrated circuits having different functions in a single package structure. Such a packaging method allows merging of heterogeneous technologies in a system-in-package (SiP) so as to systematically integrate a plurality of electronic elements having different functions, such as a memory, a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an image application processor and so on, and therefore is applicable to various thin type electronic products.
FIGS. 1A to 1F are schematic cross-sectional views showing a method for fabricating a semiconductor package 1 of a PoP structure according to the prior art.
Referring to FIG. 1A, a semiconductor element 10 such as a chip is disposed on a thermal release layer 110 of a first carrier 11. Then, an encapsulant 13 is formed on the thermal release layer 110 of the first carrier 11 for encapsulating the semiconductor element 10.
Referring to FIG. 1B, a second carrier 12 having a copper foil 120 is provided and disposed on the encapsulant 13 via the copper foil 120.
Referring to FIG. 1C, the first carrier 11 and the thermal release layer 110 are removed to expose the semiconductor element 10 and the encapsulant 13.
Referring to FIG. 1D, a plurality of through holes 130 are formed by laser in the encapsulant 13 at a periphery of the semiconductor element 10.
Referring to FIG. 1E, a plurality of conductive posts 14 are formed in the through holes 130 through the copper foil 120 by electroplating. Then, a plurality of redistribution layers 15 are formed on the encapsulant 13 and electrically connected to the conductive posts 14 and electrode pads 100 of the semiconductor element 10.
Referring to FIG. 1F, the second carrier 12 is removed. Then, a patterned circuit process is performed by using the copper foil 120 so as to form a circuit structure 16. Thereafter, a singulation process is performed.
However, in the above-described method of the semiconductor package 1, when the through holes 130 are formed by laser, walls 130a of the through holes 130 are easily scorched due to a laser thermal effect. Further, during a cleaning process of the through holes 130, the walls 130a of the through holes 130 easily collapse and present an undesired shape, as shown in FIG. 1D′, thus adversely affecting the electroplating quality of the conductive posts 14 and consequently reducing the product yield and reliability.
Therefore, how to overcome the above-described drawbacks has become critical.